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UART Registers
19.5.1.16 Transmission Control Register (TCR)
The transmission control register (TCR) stores the receive FIFO threshold levels to start/stop transmission
during hardware flow control. The transmission control register (TCR) is shown in Figure 19-49 and
described in Table 19-45.
NOTE:
• Trigger levels from 0-60 bytes are available with a granularity of 4.
• Trigger level = 4 × [4-bit register value]
• You must ensure that TCR[3:0] > TCR[7:4], whenever auto-RTS or software flow control
is enabled to avoid a misoperation of the device. In FIFO interrupt mode with flow
control, you have to also ensure that the trigger level to HALT transmission is greater or
equal to receive FIFO trigger level (either TLR[7:4] or FCR[7:6]); otherwise, FIFO
operation stalls.
• In FIFO DMA mode with flow control, this concept does not exist because the DMA
request is sent each time a byte is received.
Figure 19-49. Transmission Control Register (TCR)
15 8 7 4 3 0
Reserved RXFIFOTRIGSTART RXFIFOTRIGHALT
R-0 R/W-0 R/W-Fh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-45. Transmission Control Register (TCR) Field Descriptions
Bit Field Value Description
15-8 Reserved 0 Reserved.
7-4 RXFIFOTRIGSTART 0-Fh RX FIFO trigger level to RESTORE transmission (0 to 60).
3-0 RXFIFOTRIGHALT 0-Fh RX FIFO trigger level to HALT transmission (0 to 60).
19.5.1.17 Scratchpad Register (SPR)
The scratchpad register (SPR) is a read/write register that does not control the module. It is a scratchpad
register used to hold temporary data. The scratchpad register (SPR) is shown in Figure 19-50 and
described in Table 19-46.
Figure 19-50. Scratchpad Register (SPR)
15 8 7 0
Reserved SPR_WORD
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-46. Scratchpad Register (SPR) Field Descriptions
Bit Field Value Description
15-8 Reserved 0 Reserved.
7-0 SPR_WORD 0-FFh Scratchpad register.
3521
SPRUH73H–October 2011–Revised April 2013 Universal Asynchronous Receiver/Transmitter (UART)
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