CONTROL_MODULE Registers
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9.3.46 vdd_core_opp_050 Register (offset = 7B8h) [reset = 0h]
vdd_core_opp_050 is shown in Figure 9-49 and described in Table 9-56.
Figure 9-49. vdd_core_opp_050 Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
ntarget
R-0h
15 14 13 12 11 10 9 8
ntarget
R-0h
7 6 5 4 3 2 1 0
ntarget
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-56. vdd_core_opp_050 Register Field Descriptions
Bit Field Type Reset Description
31-24 Reserved R 0h
23-0 ntarget R 0h Ntarget value for CORE Voltage domain OPP50
Reset value is device-dependent.
810
Control Module SPRUH73H–October 2011–Revised April 2013
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