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Interrupt Controller Registers
6.5.1.10 INTC_FIQ_PRIORITY Register (offset = 64h) [reset = FFFFFFC0h]
INTC_FIQ_PRIORITY is shown in Figure 6-13 and described in Table 6-13.
This register supplies the currently active FIQ priority level
Figure 6-13. INTC_FIQ_PRIORITY Register
31 30 29 28 27 26 25 24
SpuriousFIQflag
R-1FFFFFFh
23 22 21 20 19 18 17 16
SpuriousFIQflag
R-1FFFFFFh
15 14 13 12 11 10 9 8
SpuriousFIQflag
R-1FFFFFFh
7 6 5 4 3 2 1 0
SpuriousFIQflag FIQPriority
R-1FFFFFFh R-40h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-13. INTC_FIQ_PRIORITY Register Field Descriptions
Bit Field Type Reset Description
31-7 SpuriousFIQflag R 1FFFFFFh
Spurious FIQ flag
6-0 FIQPriority R 40h
Current FIQ priority
215
SPRUH73H–October 2011–Revised April 2013 Interrupts
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