Ethernet Subsystem Registers
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14.5.10.10 MDIO User Command Complete Interrupt Mask Clear Register (MDIOUSERINTMASKCLR)
The MDIO user interrupt mask clear register (MDIOUSERINTMASKCLR) is shown in Figure 14-241 and
described in Table 14-260.
Figure 14-241. MDIO User Command Complete Interrupt Mask Clear Register
(MDIOUSERINTMASKCLR)
31 16
Reserved
R-0x0
15 2 1 0
Reserved USERINTMASKCLEAR
R-0x0 RWC-0x0
LEGEND: RWC = Read/Write/Clear; R = Read only; -n = value after reset
Table 14-260. MDIO User Command Complete Interrupt Mask Clear Register
(MDIOUSERINTMASKCLR) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved.
1-0 USERINTMASKCLEAR 0-3h MDIO user command complete interrupt mask clear for USERINTMASKED, respectively.
Writing a bit to 1 will disable further user command complete interrupts for that particular
MDIOUSERACCESSn register. Writing a 0 to this register has no effect.
1480
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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