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CONTROL_MODULE Registers
9.3.7 mpu_sldo_ctrl Register (offset = 42Ch) [reset = 0h]
mpu_sldo_ctrl is shown in Figure 9-10 and described in Table 9-17.
Figure 9-10. mpu_sldo_ctrl Register
31 30 29 28 27 26 25 24
Reserved vset
R/W-0h R/W-0h
23 22 21 20 19 18 17 16
vset
R/W-0h
15 14 13 12 11 10 9 8
Reserved
R/W-0h
7 6 5 4 3 2 1 0
Reserved
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-17. mpu_sldo_ctrl Register Field Descriptions
Bit Field Type Reset Description
31-26 Reserved R/W 0h
25-16 vset R/W 0h Trims VDDAR
15-0 Reserved R/W 0h
769
SPRUH73H–October 2011–Revised April 2013 Control Module
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