Appendix A
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11.4.2.7.18 Destination FIFO Destination Address B-Reference (DFDSTBREFn)
The destination FIFO destination address B-reference register (DFDSTBREFn) is shown in Figure 11-132
and described in Table 11-117.
Figure 11-132. Destination FIFO Destination Address B-Reference Register (DFDSTBREFn)
31 16
DADDRBREF
R-0
15 0
DADDRBREF
R-0
LEGEND: R = Read only; -n = value after reset
Table 11-117. Destination FIFO Destination Address B-Reference Register (DFDSTBREFn) Field
Descriptions
Bit Field Value Description
31-0 DADDRBREF 0-FFFF FFFFh Destination address reference for the destination FIFO register set. Represents the starting
address for the array currently being written.
11.5 Appendix A
11.5.1 Debug Checklist
This section lists some tips to keep in mind while debugging applications using the EDMA3.
The following table provides some common issues and their probable causes and resolutions.
Table 11-118. Debug List
Issue Description/Solution
The transfer associated with the channel The EDMA3CC may not service a transfer request, even though the associated
does not happen. The channel does not PaRAM set is programmed appropriately. Check for the following:
get serviced. 1) Verify that events are enabled, i.e., if an external/peripheral event is latched in Event
Registers (ER/ERH), make sure that the event is enabled in the Event Enable
Registers (EER/EERH). Similarly, for QDMA channels, make sure that QDMA events
are appropriately enabled in the QDMA Event Enable Register (QEER).
2) Verify that the DMA or QDMA Secondary Event Register (SER/SERH/QSERH) bits
corresponding to the particular event or channel are not set.
The Secondary Event Registers bits are It is possible that a trigger event was received when the parameter set associated with
set, not allowing additional transfers to the channel/event was a NULL set for a previous transfer on the channel. This is
occur on a channel. typical in two cases:
1) QDMA channels: Typically if the parameter set is non-static and expected to be
terminated by a NULL set (i.e., OPT.STATIC = 0, LINK = 0xFFFF), the parameter set is
updated with a NULL set after submission of the last TR. Because QDMA channels are
auto-triggered, this update caused the generation of an event. An event generated for a
NULL set causes an error condition and results in setting the bits corresponding to the
QDMA channel in the QEMR and QSER. This will disable further prioritization of the
channel.
2) DMA channels used in a continuous mode: The peripheral may be set up to
continuously generate infinite events (for instance, in case of McASP, every time the
data shifts out from the DXR register, it generates an XEVT). The parameter set may
be programmed to expect only a finite number of events and to be terminated by a
NULL link. After the expected number of events, the parameter set is reloaded with a
NULL parameter set. Because the peripheral will generate additional events, an error
condition is set in the SER.Ex and EMR.Ex set, preventing further event prioritization.
You must ensure that the number of events received is limited to the expected number
of events for which the parameter set is programmed, or you must ensure that bits
corresponding to particular channel or event are not set in the Secondary event
registers (SER/SERH/QSER) and Event Missed Registers (EMR/EMRH/QEMR) before
trying to perform subsequent transfers for the event/channel.
1018
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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