Texas Instruments AM335 Series Technical Reference Manual

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22.4 McASP Registers
22.4.1 McASP CFG Registers
Control registers for the McASP are summarized in Table 22-10. The control registers are accessed
through the configuration bus of the device. The receive buffer registers (RBUFn) and transmit buffer
registers (XBUFn) can also be accessed through the data port of the device, as listed in Table 22-53.
Control registers for the McASP Audio FIFO (AFIFO) are summarized in Table 22-11. Note that the AFIFO
Write FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO
control registers are accessed through the peripheral configuration port.
Table 22-10. McASP Registers Accessed Through Configuration Bus
Offset Acronym Register Description Section
0h REV Revision identification register Section 22.4.1.1
04h PWRIDLESYS Power Idle SYSCONFIG Register Section 22.4.1.2
CONFIG
10h PFUNC Pin function register Section 22.4.1.3
14h PDIR Pin direction register Section 22.4.1.4
18h PDOUT Pin data output register Section 22.4.1.5
1Ch PDIN Read returns: Pin data input register Section 22.4.1.6
1Ch PDSET Writes affect: Pin data set register (alternate write address: PDOUT) Section 22.4.1.7
20h PDCLR Pin data clear register (alternate write address: PDOUT) Section 22.4.1.8
44h GBLCTL Global control register Section 22.4.1.9
48h AMUTE Audio mute control register Section 22.4.1.10
4Ch DLBCTL Digital loopback control register Section 22.4.1.11
50h DITCTL DIT mode control register Section 22.4.1.12
60h RGBLCTL Receiver global control register: Alias of GBLCTL, only receive bits are Section 22.4.1.13
affected - allows receiver to be reset independently from transmitter
64h RMASK Receive format unit bit mask register Section 22.4.1.14
68h RFMT Receive bit stream format register Section 22.4.1.15
6Ch AFSRCTL Receive frame sync control register Section 22.4.1.16
70h ACLKRCTL Receive clock control register Section 22.4.1.17
74h AHCLKRCTL Receive high-frequency clock control register Section 22.4.1.18
78h RTDM Receive TDM time slot 0-31 register Section 22.4.1.19
7Ch RINTCTL Receiver interrupt control register Section 22.4.1.20
80h RSTAT Receiver status register Section 22.4.1.21
84h RSLOT Current receive TDM time slot register Section 22.4.1.22
88h RCLKCHK Receive clock check control register Section 22.4.1.23
8Ch REVTCTL Receiver DMA event control register Section 22.4.1.24
A0h XGBLCTL Transmitter global control register. Alias of GBLCTL, only transmit bits Section 22.4.1.25
are affected - allows transmitter to be reset independently from receiver
A4h XMASK Transmit format unit bit mask register Section 22.4.1.26
A8h XFMT Transmit bit stream format register Section 22.4.1.27
ACh AFSXCTL Transmit frame sync control register Section 22.4.1.28
B0h ACLKXCTL Transmit clock control register Section 22.4.1.29
B4h AHCLKXCTL Transmit high-frequency clock control register Section 22.4.1.30
B8h XTDM Transmit TDM time slot 0-31 register Section 22.4.1.31
BCh XINTCTL Transmitter interrupt control register Section 22.4.1.32
C0h XSTAT Transmitter status register Section 22.4.1.33
C4h XSLOT Current transmit TDM time slot register Section 22.4.1.34
C8h XCLKCHK Transmit clock check control register Section 22.4.1.35
CCh XEVTCTL Transmitter DMA event control register Section 22.4.1.36
3826
Multichannel Audio Serial Port (McASP) SPRUH73H–October 2011–Revised April 2013
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Texas Instruments AM335 Series Specifications

General

Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English