DCAN Registers
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23.4.6 TEST Register (offset = 14h) [reset = 0h]
TEST is shown in Figure 23-24 and described in Table 23-19.
For all test modes, the test bit in CAN control register needs to be set to one. If test bit is set, the RDA,
EXL, Tx1, Tx0, LBack and Silent bits are writable. Bit Rx monitors the state of pin CAN_RX and therefore
is only readable. All test register functions are disabled when test bit is cleared. The test register is only
writable if test bit in CAN control register is set. Setting Tx[1:0] other than '00' will disturb message
transfer. When the internal loop-back mode is active (bit LBack is set), bit EXL will be ignored.
Figure 23-24. TEST Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved RDA EXL
R-0h R/WP-0h R/WP-0h
7 6 5 4 3 2 1 0
Rx Tx[1:0] LBack Silent Reserved
R-0h R/WP-0h R/WP-0h R/WP-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 23-19. TEST Register Field Descriptions
Bit Field Type Reset Description
31-10 Reserved R 0h
9 RDA R/WP 0h
RAM direct access enable
0x0 = Normal operation
0x1 = Direct access to the RAM is enabled while in test mode
8 EXL R/WP 0h
External loopback mode
0x0 = Disabled
0x1 = Enabled
7 Rx R 0h Receive pin.
Monitors the actual value of the CAN_RX pin
0x0 = The CAN bus is dominant
0x1 = The CAN bus is recessive
6-5 Tx[1:0] R/WP 0h
Control of CAN_TX pin.
0x00 = Normal operation, CAN_TX is controlled by the CAN core.
0x01 = Sample point can be monitored at CAN_TX pin.
0x10 = CAN_TX pin drives a dominant value.
0x11 = CAN_TX pin drives a recessive value.
4 LBack R/WP 0h
Loopback mode
0x0 = Disabled
0x1 = Enabled
3 Silent R/WP 0h
Silent mode
0x0 = Disabled
0x1 = Enabled
2-0 Reserved R 0h
3932
Controller Area Network (CAN) SPRUH73H–October 2011–Revised April 2013
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