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Power, Reset, and Clock Management
8.1.12.2.32 CM_CLKDCOLDO_DPLL_PER Register (offset = 7Ch) [reset = 0h]
CM_CLKDCOLDO_DPLL_PER is shown in Figure 8-115 and described in Table 8-123.
This register provides controls over the digitally controlled oscillator output of the PER DPLL.
Figure 8-115. CM_CLKDCOLDO_DPLL_PER Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved DPLL_CLKDCOLDO_ Reserved ST_DPLL_CLKDCOL DPLL_CLKDCOLDO_
PWDN DO GATE_CTRL
R-0h R/W-0h R-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-123. CM_CLKDCOLDO_DPLL_PER Register Field Descriptions
Bit Field Type Reset Description
31-13 Reserved R 0h
12 DPLL_CLKDCOLDO_PW R/W 0h
Automatic power down for CLKDCOLDO o/p when it is gated
DN
0x0 = ALWAYS_ACTIVE : Keep CLKDCOLDO o/p powered on even
when it is gated
0x1 = AUTO_PWDN : Automatically power down CLKDCOLDO o/p
when it is gated.
11-10 Reserved R 0h
9 ST_DPLL_CLKDCOLDO R 0h
DPLL CLKDCOLDO status
0x0 = CLK_ENABLED : The clock output is enabled
0x1 = CLK_GATED : The clock output is gated
8 DPLL_CLKDCOLDO_GA R/W 0h
Control gating of DPLL CLKDCOLDO
TE_CTRL
0x0 = CLK_AUTOGATE : Automatically gate this clock when there is
no dependency for it
0x1 = CLK_ENABLE : Force this clock to stay enabled even if there
is no request
7-0 Reserved R 0h
647
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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