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Functional Description
• RTDM/XTDM: Program RTDMS0/XTDMS0 to 1 to indicate one active slot only. Leave other fields at
default.
• RINTCTL/XINTCTL: Program all fields according to interrupts desired.
• RCLKCHK/XCLKCHK: Not applicable. Leave at default.
• SRCTLn: Program SRMOD to inactive/transmitter/receiver as desired. DISMOD is not applicable and
should be left at default.
• DITCSRA[n], DITCSRB[n], DITUDRA[n], DITUDRB[n]: Not applicable. Leave at default.
22.3.8.2 Time-Division Multiplexed (TDM) Transfer Mode
The McASP time-division multiplexed (TDM) transfer mode supports the TDM format discussed in
Section 22.3.3.1.
Transmitting data in the TDM transfer mode requires a minimum set of pins:
• ACLKX - transmit bit clock.
• AFSX - transmit frame sync (or commonly called left/right clock).
• One or more serial data pins, AXRn, whose serializers have been configured to transmit.
The transmitter has the option to receive the ACLKX bit clock as an input, or to generate the ACLKX bit
clock by dividing down the AHCLKX high-frequency master clock. The transmitter can either generate
AHCLKX internally or receive AHCLKX as an input. See Section 22.3.5.1.
Similarly, to receive data in the TDM transfer mode requires a minimum set of pins:
• ACLKR - receive bit clock.
• AFSR - receive frame sync (or commonly called left/right clock).
• One or more serial data pins, AXRn, whose serializers have been configured to receive.
The receiver has the option to receive the ACLKR bit clock as an input or to generate the ACLKR bit clock
by dividing down the AHCLKR high-frequency master clock. The receiver can either generate AHCLKR
internally or receive AHCLKR as an input. See Section 22.3.5.2 and Section 22.3.5.3.
The control registers must be configured as follows for the TDM mode. The TDM mode specific bit fields
are in bold face:
• PFUNC: The clock, frame, data pins must be configured for McASP function.
• PDIR: The clock, frame, data pins must be configured to the direction desired.
• PDOUT, PDIN, PDSET, PDCLR: Not applicable. Leave at default.
• GBLCTL: Follow the initialization sequence in Section 22.3.12.2 to configure this register.
• AMUTE: Program all fields according to mute control desired.
• DLBCTL: If loopback mode is desired, configure this register according to Section 22.3.10.5, otherwise
leave this register at default.
• DITCTL: DITEN must be left at default 0 to select TDM mode. Leave the register at default.
• RMASK/XMASK: Mask desired bits according to Section 22.3.9.2 and Section 22.3.10.3.
• RFMT/XFMT: Program all fields according to data format desired. See Section 22.3.10.3.
• AFSRCTL/AFSXCTL: Set RMOD/XMOD bits to 2-32 for TDM mode. Configure other fields as desired.
• ACLKRCTL/ACLKXCTL: Program all fields according to bit clock desired. See Section 22.3.5.
• AHCLKRCTL/AHCLKXCTL: Program all fields according to high-frequency clock desired. See
Section 22.3.5.
• RTDM/XTDM: Program all fields according to the time slot characteristics desired.
• RINTCTL/XINTCTL: Program all fields according to interrupts desired.
• RCLKCHK/XCLKCHK: Program all fields according to clock checking desired.
• SRCTLn: Program all fields according to serializer operation desired.
• DITCSRA[n], DITCSRB[n], DITUDRA[n], DITUDRB[n]: Not applicable. Leave at default.
3789
SPRUH73H–October 2011–Revised April 2013 Multichannel Audio Serial Port (McASP)
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