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Power, Reset, and Clock Management
8.1.12.2.14 CM_IDLEST_DPLL_DDR Register (offset = 34h) [reset = 0h]
CM_IDLEST_DPLL_DDR is shown in Figure 8-97 and described in Table 8-105.
This register allows monitoring the master clock activity. This register is read only and automatically
updated. [warm reset insensitive]
Figure 8-97. CM_IDLEST_DPLL_DDR Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved ST_MN_BYPASS
R-0h R-0h
7 6 5 4 3 2 1 0
Reserved ST_DPLL_CLK
R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-105. CM_IDLEST_DPLL_DDR Register Field Descriptions
Bit Field Type Reset Description
31-9 Reserved R 0h
8 ST_MN_BYPASS R 0h
DPLL MN_BYPASS status
0x0 = NO_MNBYPASS : DPLL is not in MN_Bypass
0x1 = MN_BYPASS : DPLL is in MN_Bypass
7-1 Reserved R 0h
0 ST_DPLL_CLK R 0h
DPLL clock activity
0x0 = DPLL_UNLOCKED : DPLL is either in bypass mode or in stop
mode.
0x1 = DPLL_LOCKED : DPLL is LOCKED
629
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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