Contents
Preface .................................................................................................................................... 149
1 Introduction .................................................................................................................... 150
1.1 AM335x Family ........................................................................................................... 150
1.1.1 Device Features ................................................................................................. 150
1.1.2 Device Identification ............................................................................................ 151
1.1.3 Feature Identification ........................................................................................... 151
1.2 Silicon Revision Functional Differences and Enhancements ....................................................... 153
1.2.1 Added RTC Alarm Wakeup for DeepSleep Modes ......................................................... 153
1.2.2 Changed BOOTP Identifier .................................................................................... 153
1.2.3 Changed Product String in USB Descriptor ................................................................. 153
1.2.4 Added DPLL Power Switch Control and Status Registers ................................................ 153
1.2.5 Added Control for CORE SRAM LDO Retention Mode .................................................... 153
1.2.6 Added Pin Mux Options for GPMC_A9 to Facilitate RMII Pin Muxing ................................... 153
1.2.7 Changed Polarity of Input Signal nNMI (Pin EXTINTn) .................................................... 153
1.2.8 Changed Default Value of ncin and pcin Bits in vtp_ctrl Register ........................................ 154
1.2.9 Changed Default Value of RGMII Mode to No Internal Delay ............................................ 154
1.2.10 Changed Default Value of RMII Clock Source ............................................................. 154
1.2.11 Changed the Method of Determining Speed of Operation During EMAC Boot ........................ 154
1.2.12 Added EFUSE_SMA Register for Help Identifying Different Device Variants ......................... 154
2 Memory Map ................................................................................................................... 155
2.1 ARM Cortex-A8 Memory Map .......................................................................................... 155
3 ARM MPU Subsystem ....................................................................................................... 164
3.1 ARM Cortex-A8 MPU Subsystem ...................................................................................... 165
3.1.1 Features .......................................................................................................... 166
3.1.2 MPU Subsystem Integration ................................................................................... 166
3.1.3 MPU Subsystem Clock and Reset Distribution ............................................................. 167
3.1.4 ARM Subchip .................................................................................................... 170
3.1.5 Interrupt Controller .............................................................................................. 171
3.1.6 Power Management ............................................................................................ 171
3.1.7 ARM Programming Model ..................................................................................... 174
4 Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) ............. 176
4.1 Introduction ............................................................................................................... 177
5 Graphics Accelerator (SGX) .............................................................................................. 178
5.1 Introduction ............................................................................................................... 179
5.1.1 POWERVR SGX Main Features .............................................................................. 179
5.1.2 SGX 3D Features ............................................................................................... 179
5.1.3 Universal Scalable Shader Engine (USSE) – Key Features .............................................. 180
5.1.4 Unsupported Features .......................................................................................... 181
5.2 Integration ................................................................................................................. 182
5.2.1 SGX530 Connectivity Attributes ............................................................................... 182
5.2.2 SGX530 Clock and Reset Management ..................................................................... 182
5.2.3 SGX530 Pin List ................................................................................................. 183
5.3 Functional Description ................................................................................................... 184
5.3.1 SGX Block Diagram ............................................................................................ 184
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Contents SPRUH73H–October 2011–Revised April 2013
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