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Touchscreen Controller Registers
12.5.1.17 TS_CHARGE_STEPCONFIG Register (offset = 5Ch) [reset = 0h]
TS_CHARGE_STEPCONFIG is shown in Figure 12-21 and described in Table 12-21.
TS Charge StepConfiguration@TSC_ADC_SS_TS_Charge_StepConfig Register
Figure 12-21. TS_CHARGE_STEPCONFIG Register
31 30 29 28 27 26 25 24
Reserved Diff_CNTRL SEL_RFM__SWC_1_
0
R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
SEL_RFM__SWC_1_ SEL_INP_SWC_3_0 SEL_INM_SWM3_0
0
R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
SEL_INM_SWM3_0 SEL_RFP__SWC_2_0 WPNSW_SWC YPNSW_SWC XNPSW_SWC YNNSW_SWC
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
YPPSW__SWC XNNSW__SWC XPPSW_SWC Reserved
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-21. TS_CHARGE_STEPCONFIG Register Field Descriptions
Bit Field Type Reset Description
31-26 Reserved R/W 0h
25 Diff_CNTRL R/W 0h Differential Control Pin.
0 = Single Ended.
1 = Differential Pair Enable.
24-23 SEL_RFM__SWC_1_0 R/W 0h SEL_RFM pins SW configuration.
00 = VSSA.
01 = XNUR.
10 = YNLR.
11 = VREFN.
22-19 SEL_INP_SWC_3_0 R/W 0h SEL_INP pins SW configuration.
0000 = Channel 1.
0111 = Channel 8.
1xxx = VREFN.
18-15 SEL_INM_SWM3_0 R/W 0h SEL_INM pins for neg differential.
0000 = Channel 1.
0111 = Channel 8.
1xxx = VREFN.
14-12 SEL_RFP__SWC_2_0 R/W 0h SEL_RFP pins SW configuration.
000 = VDDA.
001 = XPUL.
010 = YPLL.
011 = VREFP.
1xx = INTREF.
11 WPNSW_SWC R/W 0h
WPNSW pin SW configuration
10 YPNSW_SWC R/W 0h
YPNSW pin SW configuration
9 XNPSW_SWC R/W 0h
XNPSW pin SW configuration
8 YNNSW_SWC R/W 0h
YNNSW pin SW configuration
7 YPPSW__SWC R/W 0h
YPPSW pin SW configuration
6 XNNSW__SWC R/W 0h
XNNSW pin SW configuration
5 XPPSW_SWC R/W 0h
XPPSW pin SW configuration
4-0 Reserved R/W 0h
1055
SPRUH73H–October 2011–Revised April 2013 Touchscreen Controller
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