Ethernet Subsystem Registers
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Figure 14-234. PHY Acknowledge Status Register (MDIOALIVE)
31 0
ALIVE
RWC-0x0
LEGEND: RWC = Read/Write/Clear
Table 14-253. PHY Acknowledge Status Register (MDIOALIVE) Field Descriptions
Bit Field Value Description
31-0 ALIVE 0-FFFF FFFFh MDIO alive. Each of the 32 bits of this register is set if the most recent access to the PHY
with address corresponding to the register bit number was acknowledged by the PHY, the
bit is reset if the PHY fails to acknowledge the access. Both the user and polling
accesses to a PHY will cause the corresponding alive bit to be updated. The alive bits are
only meant to be used to give an indication of the presence or not of a PHY with the
corresponding address. Writing a 1 to any bit will clear it, writing a 0 has no effect.
14.5.10.4 PHY Link Status Register (MDIOLINK)
The PHY link status register (MDIOLINK) is shown in Figure 14-235 and described in Table 14-254.
Figure 14-235. PHY Link Status Register (MDIOLINK)
31 0
LINK
R-0x0
LEGEND: R = Read only; -n = value after reset
Table 14-254. PHY Link Status Register (MDIOLINK) Field Descriptions
Bit Field Value Description
31-0 LINK 0-FFFF FFFFh MDIO link state. This register is updated after a read of the Generic Status Register of a
PHY. The bit is set if the PHY with the corresponding address has link and the PHY
acknowledges the read transaction. The bit is reset if the PHY indicates it does not have
link or fails to acknowledge the read transaction. Writes to the register have no effect. In
addition, the status of the two PHYs specified in the MDIOUSERPHYSELn registers can
be determined using the MLINK input pins. This is determined by the LINKSEL bit in the
MDIOUSERPHYSELn register.
1476
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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