Public RAM
0x402F0400 (GP)
RAM Exc. Vectors
6KB Public stack
Tracing Data
0x4030FFFF
0x4030CE00
0x4030B800
Downloaded Image
Static Variables
0x402F0400
Functional Description
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26.1.3.2 Public RAM Memory Map
The Public ROM Code makes use of the on chip RAM module connected to the L3 interconnect (further
referred to as L3 RAM). Its usage is shown in Figure 26-4. The Public RAM memory map ranges from
address 402F0400h to 4030FFFFh on a GP Device.
Figure 26-4. Public RAM Memory Map
Download Image
This area is used by the Public ROM Code to store the downloaded boot image. It can be up to 109KB.
Public Stack
Space reserved for stack.
RAM Exception Vectors
The RAM exception vectors enable a simple means for redirecting exceptions to custom handlers.
Table 26-3 shows content of the RAM space reserved for RAM vectors. The first seven addresses are
ARM instructions which load the value located in the subsequent seven addresses into the PC register.
Theses instructions are executed when an exception occurs since they are called from the ROM exception
vectors. Undefined, SWI, Unused and FIQ exceptions are redirected to a hardcoded dead loop. Pre-fetch
abort, data abort, and IRQ exception are redirected to pre-defined ROM handlers. User code can redirect
any exception to a custom handler either by writing its address to the appropriate location from
4030CE24h to 4030CE3Ch or by overriding the branch (load into PC) instruction between addresses from
4030CE04h to 4030CE1Ch.
Table 26-3. RAM Exception Vectors
Address Exception Content
4030CE00h Reserved Reserved
4030CE04h Undefined PC = [4030CE24h]
4030CE08h SWI PC = [4030CE28h]
4030CE0Ch Pre-fetch abort PC = [4030CE2Ch]
4030CE10h Data abort PC = [4030CE30h]
4030CE14h Unused PC = [4030CE34h]
4030CE18h IRQ PC = [4030CE38h]
4030CE1Ch FIQ PC = [4030CE3Ch]
4030CE20h Reserved 20090h
4030CE24h Undefined 20080h
4030CE28h SWI 20084h
4100
Initialization SPRUH73H–October 2011–Revised April 2013
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