USB Registers
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16.5.5.2 TDFDQ Register (offset = 4h) [reset = 0h]
TDFDQ is shown in Figure 16-153 and described in Table 16-165.
Figure 16-153. TDFDQ Register
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved TD_DESC_QMGR TD_DESC_QNUM
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
TD_DESC_QNUM
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 16-165. TDFDQ Register Field Descriptions
Bit Field Type Reset Description
13-12 TD_DESC_QMGR R/W 0h This field controls which of the 4 Queue Managers the DMA will
access in order to allocate a channel teardown descriptor from the
teardown descriptor queue.
11-0 TD_DESC_QNUM R/W 0h This field controls which of the 2K queues in the indicated queue
manager should be read in order to allocate channel teardown
descriptors.
CPPI DMA Teardown Free Descriptor Queue Control Register
1930
Universal Serial Bus (USB) SPRUH73H–October 2011–Revised April 2013
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