Functional Description
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The allocated rates for rate-limited traffic must not be oversubscribed. For example, if port 1 is sending
15% rate limited traffic to port 2 priority 3, and port 0 is also sending 10% rate-limited traffic to port 2
priority 3, then the port 2 priority 3 egress rate must be configured to be 25% plus a percent or two for
margin. The switch must be configured to allow some percentage of non rate-limited traffic. Non-rate-
limited traffic must be configured to be sent to non rate-limited queues. No packets from the host should
be dropped, but non rate-limited traffic received on an ethernet port can be dropped. Rate-limited mode is
configured as shown:
• Set tx_in_sel[1:0] = 10 in P1/2_Tx_In_Ctl to enable ports 1 and 2 transmit FIFO inputs to be configured
for rate-limiting queues. Enabling a queue to be rate-limiting with this field affects only the packet being
loaded into the FIFO, it does not configure the transmit for queue shaping.
• Configure the number of rate-limited queues for port 1 and 2 transmit FIFO’s by setting the
tx_rate_en[3:0] field in P1/2_Tx_In_Ctl. Rate limited queues must be the highest number. For example,
if there are two rate limited queues then 1100 would be written to this field for priorities 3 and 2. This
field enables the FIFO to allow rate-limited traffic into rate-limited queues while discriminating against
non rate-limited queues.
• Set p1_priN_shape_en and p2_priN_shape_en in the CPSW_3G PTYPE register. These bits
determine which queues actually shape the output data stream. In general, the same priorities that are
set in tx_rate_en are set in these bits as well, but the FIFO input and output enable bits are separate to
allow rate-limiting from the host to non shaped channels if desired.
When queue shaping is not enabled for a queue then packets are selected for egress based on
priority. When queue shaping is enabled then packets are selected for egress based on queue
percentages. If shaping is required on a single queue then it must be priority 3 (priorities 2, 1 and 0 are
strict priority). If shaping is required on two queues then it must be on priorities 2 and 3 (priorities 1 and
0 are strict priority). If shaping is required on three queues then it must be priorities 3, 2, and 1 (priority
0 would then get the leftovers). Priority shaping follows the requirements in the IEEE P802.1Qav/D6.0
specification. Priority shaping is not compatible with priority escalation (escalation must be disabled).
• P0_Tx_In_Ctl[1:0] should remain at the default 00 value. Port 0 egress (CPDMA RX) should not be
rate-limited.
• The CPDMA is configured for rate-limited transmit (switch ingress) channels by setting the highest bits
of the tx_rlim[7:0] field in the CPDMA DMA_Control register. If there are two rate limited channels then
tx_rlim[7:0] = 11000000 (the rate limited channels must be the highest priorities). Also, tx_ptype in the
DMA_Control register must be set (fixed priority mode). Rate limited channels must go to rate-limited
FIFO queues, and the FIFO queue rate must not be oversubscribed.
14.3.2.11 Packet Padding
VLAN tagged ingress packets of 64 to 67-bytes will be padded to 64-bytes on egress (all ports) if the
VLAN is removed on egress.
14.3.2.12 Flow Control
There are two types of switch flow control – CPPI port flow control and Ethernet port flow control. The
CPPI and Ethernet port naming conventions for data flow into and out of the switch are reversed. For the
CPPI port (port 0), transmit operations move packets from external memory into the switch and then out to
either or both Ethernet transmit ports (ports 1 and 2). CPPI receive operations move packets that were
received on either or both Ethernet receive ports to external memory.
14.3.2.12.1 CPPI Port Flow Control
The CPPI port has flow control available for transmit (switch ingress). CPPI receive operations (switch
egress) do not require flow control. CPPI Transmit flow control is initiated when enabled and triggered.
CPPI transmit flow control is enabled by setting the p0_flow_en bit in the CPSW_Flow_Control register.
CPPI transmit flow control is enabled by default on reset because host packets should not be dropped in
any mode of operation.
1206
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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