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DMTimer
20.1.5.5 IRQSTATUS Register (offset = 28h) [reset = 0h]
IRQSTATUS is shown in Figure 20-13 and described in Table 20-15.
Component interrupt request status. Check the corresponding secondary status register. Enabled status is
not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status
gets cleared, that is, even if not enabled).
Figure 20-13. IRQSTATUS Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved TCAR_IT_FLAG OVF_IT_FLAG MAT_IT_FLAG
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-15. IRQSTATUS Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
2 TCAR_IT_FLAG R/W 0h
IRQ status for Capture
0x0x0(W) = No action
0x0x0(R) = No event pending
0x0x1(W) = Clear pending event, if any
0x0x1(R) = IRQ event pending
1 OVF_IT_FLAG R/W 0h
IRQ status for Overflow
0x0x0(W) = No action
0x0x0(R) = No event pending
0x0x1(W) = Clear pending event, if any
0x0x1(R) = IRQ event pending
0 MAT_IT_FLAG R/W 0h
IRQ status for Match
0x0x0(W) = No action
0x0x0(R) = No event pending
0x0x1(W) = Clear pending event, if any
0x0x1(R) = IRQ event pending
3571
SPRUH73H–October 2011–Revised April 2013 Timers
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