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Interrupt Controller Registers
6.5.1.2 INTC_SYSCONFIG Register (offset = 10h) [reset = 0h]
INTC_SYSCONFIG is shown in Figure 6-5 and described in Table 6-5.
This register controls the various parameters of the OCP interface
Figure 6-5. INTC_SYSCONFIG Register
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved Reserved Reserved SoftReset Autoidle
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-5. INTC_SYSCONFIG Register Field Descriptions
Bit Field Type Reset Description
4-3 Reserved R 0h Write 0's for future compatibility.
Reads returns 0
1 SoftReset R/W 0h Software reset.
Set this bit to trigger a module reset.
The bit is automatically reset by the hardware.
During reads, it always returns 0.
0x0(Read) = always_Always returns 0
0x1(Read) = never_never happens
0 Autoidle R/W 0h
Internal OCP clock gating strategy
0x0 = clkfree : OCP clock is free running
0x1 = autoClkGate : Automatic OCP clock gating strategy is applied,
bnased on the OCP interface activity
207
SPRUH73H–October 2011–Revised April 2013 Interrupts
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