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Power, Reset, and Clock Management
8.1.13.2.2 PM_PER_PWRSTST Register (offset = 8h) [reset = 1E60007h]
PM_PER_PWRSTST is shown in Figure 8-170 and described in Table 8-186.
This register provides a status on the current PER power domain state. [warm reset insensitive]
Figure 8-170. PM_PER_PWRSTST Register
31 30 29 28 27 26 25 24
Reserved pru_icss_mem_statest
R-0h R-3h
23 22 21 20 19 18 17 16
pru_icss_mem_statest ram_mem_statest InTransition Reserved PER_mem_statest Reserved
R-3h R-3h R-0h R-0h R-3h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved LogicStateSt PowerStateSt
R-0h R-1h R-3h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-186. PM_PER_PWRSTST Register Field Descriptions
Bit Field Type Reset Description
31-25 Reserved R 0h
24-23 pru_icss_mem_statest R 3h
PRU-ICSS memory state status
0x0 = Mem_off : Memory is OFF
0x2 = Reserved : Reserved
0x3 = Mem_on : Memory is ON
22-21 ram_mem_statest R 3h
OCMC RAM memory state status
0x0 = Mem_off : Memory is OFF
0x2 = Reserved : Reserved
0x3 = Mem_on : Memory is ON
20 InTransition R 0h
Domain transition status
0x0 = No : No on-going transition on power domain
0x1 = Ongoing : Power domain transition is in progress.
19 Reserved R 0h
18-17 PER_mem_statest R 3h
PER domain memory state status
0x0 = Mem_off : Memory is OFF
0x2 = Reserved : Reserved
0x3 = Mem_on : Memory is ON
16-3 Reserved R 0h
2 LogicStateSt R 1h
Logic state status
0x0 = OFF : Logic in domain is OFF
0x1 = ON : Logic in domain is ON
1-0 PowerStateSt R 3h
Current Power State Status
0x0 = OFF : OFF State
0x1 = RET
0x2 = Reserved1
0x3 = ON : ON State
713
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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