Interrupt Controller Registers
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6.5.1.37 INTC_MIR3 Register (offset = E4h) [reset = FFFFFFFFh]
INTC_MIR3 is shown in Figure 6-40 and described in Table 6-40.
This register contains the interrupt mask
Figure 6-40. INTC_MIR3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mir
R/W-FFFFFFFFh
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-40. INTC_MIR3 Register Field Descriptions
Bit Field Type Reset Description
31-0 Mir R/W FFFFFFFFh
Interrupt mask
242
Interrupts SPRUH73H–October 2011–Revised April 2013
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