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7.3.6.7 DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0)
The DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0) is shown in the figure and table below..
Figure 7-134. DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0)
31 16
Reserved
R-0
15 1 0
Reserved WRLVL_INIT_MODE_S
EL
R-0 W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-157. DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0)
Bit Field Value Description
31-1 Reserved 0 Reserved
0 WRLVL_INIT_MO The user programmable init ratio selection mode for Write Leveling FSM.
DE_SEL
0 Selects a starting ratio value based on Write Leveling of previous data slice.
1 Selects a starting ratio value based in register DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0 value
programmed by the user.
7.3.6.8 DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0)
The DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0) is shown in the figure and table below.
Figure 7-135. DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0)
31 20 19 16
Reserved Reserved
R-0 R-0
15 10 9 0
Reserved GATELVL_INIT_RATIO_CS0
R-0 W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-158. DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0) Field Descriptions
Bit Field Value Description
31-20 Reserved Reserved
19-10 Reserved 0h Reserved
9-0 GATELVL_INIT_RATIO_CS0 0h The user programmable init ratio used by DQS Gate Training FSM when
DATA0/1/_REG_PHY_GATELVL_INIT_MODE_0 register value set to 1.
472
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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