McASP Registers
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Table 22-32. Receiver Status Register (RSTAT) Field Descriptions (continued)
Bit Field Value Description
1 RSYNCERR Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync (AFSR) occurs
before it is expected. Causes a receive interrupt (RINT), if this bit is set and RSYNCERR in RINTCTL is
set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect.
0 Unexpected receive frame sync did not occur.
1 Unexpected receive frame sync did occur.
0 ROVRN Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from
XRSR to RBUF, but the former data in RBUF has not yet been read by the CPU or DMA. Causes a
receive interrupt (RINT), if this bit is set and ROVRN in RINTCTL is set. This bit is cleared by writing a 1
to this bit. Writing a 0 to this bit has no effect.
0 Receiver overrun did not occur.
1 Receiver overrun did occur.
22.4.1.22 Current Receive TDM Time Slot Registers (RSLOT)
The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data
frame. The RSLOT is shown in Figure 22-60 and described in Table 22-33.
Figure 22-60. Current Receive TDM Time Slot Registers (RSLOT)
31 16
Reserved
R-0
15 9 8 0
Reserved RSLOTCNT
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 22-33. Current Receive TDM Time Slot Registers (RSLOT) Field Descriptions
Bit Field Value Description
31-9 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
8-0 RSLOTCNT 0-17Fh Current receive time slot count. Legal values: 0 to 383 (17Fh).
TDM function is not supported for > 32 time slots. However, TDM time slot counter may count to 383
when used to receive a DIR block (transferred over TDM format).
3858
Multichannel Audio Serial Port (McASP) SPRUH73H–October 2011–Revised April 2013
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