Power, Reset, and Clock Management
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Modulation frequency (f
m
) can be programmed as a ratio of Fref / 4; that is, the value that needs to be
programmed ModFreqDivider = Fref / (4*f
m
). The ModFreqDivider is split into Mantissa and 2^Exponent
(ModFreqDivider = ModFreqDividerMantissa * 2^ModFreqDividerExponent). The mantissa is controlled by
7-bit signal ModFreqDividerMantissa through
CM_SSC_MODFREQDIV_DPLL_xxx.MODFREQDEV_MANTISSA bit field. The exponent is controlled by
3bit signal ModFreqDividerExponent through the
CM_SSC_MODFREQDIV_DPLL_xxx.MODFREQDEV_EXPONENT bit field.
Note: Although the same value of ModFreqDivider can be obtained by different combinations of mantissa
and exponent values, it is recommended to get the target ModFreqDivider by programming maximum
mantissa and a minimum exponent. To define the Frequency spread (Δf), ΔM must be controlled as
explained previously. To define ΔM, the step size of M for each Fref during the triangular pattern must be
programmed; that is,
ΔM = (2^ModFreqDividerExponent) * ModFreqDividerMantissa * DeltaMStep IF
ModFreqDividerExponent ≤ 3ΔM = 8 * ModFreqDividerMantissa * DeltaMStep IF
ModFreqDividerExponent > 3
DeltaMStep is split into integer part and fractional part. Integer part is controlled by 2-bit signal
DeltaMStepInteger through the CM_SSC_DELTAMSTEP_DPLL_xxx.DELTAMSTEP_INTEGER bit field.
Fractional part is controlled by 18-bit signal DeltaMStepFraction through the
CM_SSC_DELTAMSTEP_DPLL_xxx.DELTAMSTEP_FRACTION bit field.
The frequency spread achieved has an overshoot of 20 percent or an inaccuracy of +20 percent. If the
CM_CLKMODE_DPLL.DPLL_SSC_DOWNSPREADis set to 1, the frequency spread on lower side is
twice the programmed value. The frequency spread on higher side is 0 (except for the overshoot as
described previously).
There is restriction of range of M values. The restriction is M-ΔM should be ≥ 20. Also, M+ΔM should be ≤
2045. In case the downspread feature is enabled, M-2*ΔM should be ≥ 20 and M ≤ 2045.
8.1.6.7 Core PLL Description
The Core PLL provides the source for a majority of the device infrastructure and peripheral clocks. The
Core PLL comprises an ADPLLS with HSDIVIDER and additional dividers and muxes located in the
PRCM as shown in Figure 8-10.
524
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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