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Ethernet Subsystem Registers
14.5.10.9 MDIO User Command Complete Interrupt Mask Set Register (MDIOUSERINTMASKSET)
The MDIO user command complete interrupt mask set register (MDIOUSERINTMASKSET) is shown in
Figure 14-240 and described in Table 14-259.
Figure 14-240. MDIO User Command Complete Interrupt Mask Set Register
(MDIOUSERINTMASKSET)
31 16
Reserved
R-0x0
15 2 1 0
Reserved USERINTMASKSET
R-0x0 RWC-0x0
LEGEND: RWC = Read/Write/Clear; R = Read only; -n = value after reset
Table 14-259. MDIO User Command Complete Interrupt Mask Set Register
(MDIOUSERINTMASKSET) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved.
1-0 USERINTMASKSET 0-3h MDIO user interrupt mask set for USERINTMASKED, respectively. Writing a bit to 1 will
enable MDIO user command complete interrupts for that particular MDIOUSERACCESSn
register. MDIO user interrupt for a particular MDIOUSERACCESSn register is disabled if
the corresponding bit is 0. Writing a 0 to this register has no effect.
1479
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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