SYNCI
PRDEQ
Disable
Disable
Sync out
select
ECCTL2[SYNCOSEL]
SYNCO
ECCTL2[SWSYNC]
SYNC
ECCTL2[SYNCI_EN]
CTRPHS
LD_CTRPHS
CLK
TSCTR
(counter 32b)
RST
OVF
SYSCLK
Delta−mode
CNTOVF
CTR[31−0]
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Enhanced Capture (eCAP) Module
15.3.2.2.4 32-Bit Counter and Phase Control
This counter (Figure 15-106) provides the time-base for event captures, and is clocked via the system
clock.
A phase register is provided to achieve synchronization with other counters, via a hardware and software
forced sync. This is useful in APWM mode when a phase offset between modules is needed.
On any of the four event loads, an option to reset the 32-bit counter is given. This is useful for time
difference capture. The 32-bit counter value is captured first, then it is reset to 0 by any of the LD1-LD4
signals.
Figure 15-106. Counter and Synchronization Block Diagram
1613
SPRUH73H–October 2011–Revised April 2013 Pulse-Width Modulation Subsystem (PWMSS)
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