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Functional Description
14.3.3 Ethernet Mac Sliver (CPGMAC_SL)
The CPGMAC_SL peripheral shall be compliant to the IEEE Std 802.3 Specification. Half duplex mode is
supported in 10/100 Mbps mode, but not in 1000 Mbps (gigabit) mode.
Features:
• Synchronous 10/100/1000 Mbit operation.
• G/MII Interface.
• Hardware Error handling including CRC.
• Full Duplex Gigabit operation (half duplex gigabit is not supported).
• EtherStats and 802.3Stats RMON statistics gathering support for external statistics collection module.
• Transmit CRC generation selectable on a per channel basis.
• Emulation Support.
• VLAN Aware Mode Support.
• Hardware flow control.
• Programmable Inter Packet Gap (IPG)
14.3.3.1 GMII/MII Media Independent Interface
The following sections cover operation of the Media Independent Interface in 10/100/1000 Mbps modes.
An IEEE 802.3 compliant Ethernet MAC controls the interface.
14.3.3.1.1 Data Reception
14.3.3.1.1.1 Receive Control
Data received from the PHY is interpreted and output. Interpretation involves detection and removal of the
preamble and start of frame delimiter, extraction of the address and frame length, data handling, error
checking and reporting, cyclic redundancy checking (CRC), and statistics control signal generation.
14.3.3.1.1.2 Receive Inter-Frame Interval
The 802.3 required inter-packet gap (IPG) is 24 GMII clocks (96 bit times) for 10/100 Mbit modes, and 12
GMII clocks (96 bit times) for 1000 Mbit mode. However, the MAC can tolerate a reduced IPG (2 GMII
clocks in 10/100 mode and 5 GMII clocks in 1000 mode) with a correct preamble and start frame delimiter.
This interval between frames must comprise (in the following order):
• An Inter-Packet Gap (IPG).
• A seven octet preamble (all octets 0x55).
• A one octet start frame delimiter (0x5D).
14.3.3.1.2 Data Transmission
The Gigabit Ethernet Mac Sliver (GMII) passes data to the PHY when enabled. Data is synchronized to
the transmit clock rate. The smallest frame that can be sent is two bytes of data with four bytes of CRC (6
byte frame).
14.3.3.1.2.1 Transmit Control
A jam sequence is output if a collision is detected on a transmit packet. If the collision was late (after the
first 64 bytes have been transmitted) the collision is ignored. If the collision is not late, the controller will
back off before retrying the frame transmission. When operating in full duplex mode the carrier sense
(CRS) and collision sensing modes are disabled.
1223
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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