Power, Reset, and Clock Management
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8.1.13.7.1 PM_GFX_PWRSTCTRL Register (offset = 0h) [reset = 60044h]
PM_GFX_PWRSTCTRL is shown in Figure 8-189 and described in Table 8-210.
This register controls the GFX power state to reach upon a domain sleep transition.
Figure 8-189. PM_GFX_PWRSTCTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved GFX_MEM_ONState Reserved
R-0h R-3h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved GFX_MEM_RETState Reserved LowPowerStateChang Reserved LogicRETState PowerState
e
R-0h R/W-1h R-0h R/W-0h R-0h R/W-1h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-210. PM_GFX_PWRSTCTRL Register Field Descriptions
Bit Field Type Reset Description
31-19 Reserved R 0h
18-17 GFX_MEM_ONState R 3h
GFX memory state when domain is ON.
16-7 Reserved R 0h
6 GFX_MEM_RETState R/W 1h
5 Reserved R 0h
4 LowPowerStateChange R/W 0h Power state change request when domain has already performed a
sleep transition.
Allows going into deeper low power state without waking up the
power domain.
0x0 = DIS : Do not request a low power state change.
0x1 = EN : Request a low power state change. This bit is
automatically cleared when the power state is effectively changed or
when power state is ON.
3 Reserved R 0h
2 LogicRETState R/W 1h
Logic state when power domain is RETENTION
0x0 = logic_off : Only retention registers are retained and remaing
logic is off when the domain is in RETENTION state.
0x1 = logic_ret : Whole logic is retained when domain is in
RETENTION state.
1-0 PowerState R/W 0h
Power state control
0x0 = OFF : OFF State
0x1 = RET
0x2 = reserved_1
0x3 = ON : ON State
740
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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