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DMTimer 1ms
20.2.3.7 Sleep Mode Request and Acknowledge
Upon a Sleep mode request issued by the host processor (the Idle Request PIOCPMIDLEREQ signal is
active), the timer module will go in Sleep mode according to the IdleMode field of the System configuration
register (see TIOCP_CFG and Ref. [4]).
If the IdleMode field sets No-Idle mode, the Timer does not go in Sleep mode and the Idle acknowledge
signal (POROCPSIDLEACK) is never asserted.
If the IdleMode field sets Force-Idle mode, the timer goes in Sleep mode independently of the internal
module state and the Idle acknowledge signal (POROCPSIDLEACK) is unconditionally asserted.
If the IdleMode field sets Smart-Idle mode, the timer module evaluates its internal capability to have the
interface/functional clock switched off. Depending on the ClockActivity field setting the timer module
evaluates the internal activity and asserts the Idle acknowledge signal (POROCPSIDLEACK), entering in
Sleep mode, ready to issue a wake-up request.
The following table describes the Smart Idle behavior according to the clock activity setting:
Table 20-32. SmartIdle - Clock Activity Field Configuration
Clock Activity Functional Clock OCP Clock Module Behavior
11 ON ON The Idle acknowledge signal is
asserted when there are no
10 ON OFF
pending activities on the OCP
clock domain, without
evaluating the pending
activities on the functional
clock domain. (The module will
enter in Sleep mode and if a
pending interrupt event is
finished during Idle mode the
wake-up signal will be
asserted).
01 OFF ON The Idle acknowledge signal is
asserted when there are no
00 OFF OFF
pending activities on the
functional and OCP clock
domains (Improved latency in
assertion of Idle acknowledge).
The Wake-up capability of the
module is disabled.
3595
SPRUH73H–October 2011–Revised April 2013 Timers
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