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EDMA3 Registers
11.4.2.2 EDMA3TC Configuration Register (TCCFG)
The EDMA3TC configuration register (TCCFG) is shown in Figure 11-106 and described in Table 11-91.
Figure 11-106. EDMA3TC Configuration Register (TCCFG)
31 16
Reserved
R-0
15 10 9 8 7 6 5 4 3 2 0
Reserved DREGDEPTH Reserved BUSWIDTH Rsvd FIFOSIZE
R-0 R-2 R-0 R-2 R-0 R-4
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = value is indeterminate after reset
Table 11-91. EDMA3TC Configuration Register (TCCFG) Field Descriptions
Bit Field Value Description
31-10 Reserved 0 Reserved.
9-8 DREGDEPTH 0-3h Destination register FIFO depth parameterization.
0 Reserved.
1h Reserved.
2h 4 entry (for TC0, TC1, TC2, and TC3)
3h Reserved.
7-6 Reserved 0 Reserved.
5-4 BUSWIDTH 0-3h Bus width parameterization.
0-1h Reserved.
2h 128-bit
3h Reserved.
3 Reserved 0 Reserved.
2-0 FIFOSIZE 0-7h FIFO size
0-1h Reserved.
2h Reserved.
3h Reserved.
4h 512 byte FIFO
5h Reserved.
6h-7h Reserved.
995
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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