Power, Reset, and Clock Management
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8.1.12.4.2 CM_MPU_MPU_CLKCTRL Register (offset = 4h) [reset = 2h]
CM_MPU_MPU_CLKCTRL is shown in Figure 8-153 and described in Table 8-163.
This register manages the MPU clocks.
Figure 8-153. CM_MPU_MPU_CLKCTRL Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved STBYST IDLEST
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-163. CM_MPU_MPU_CLKCTRL Register Field Descriptions
Bit Field Type Reset Description
31-19 Reserved R 0h
18 STBYST R 0h
Module standby status.
0x0 = Func : Module is functional (not in standby)
0x1 = Standby : Module is in standby
17-16 IDLEST R 0h
Module idle status.
0x0 = Func : Module is fully functional, including OCP
0x1 = Trans : Module is performing transition: wakeup, or sleep, or
sleep abortion
0x2 = Idle : Module is in Idle mode (only OCP part). It is functional if
using separate functional clock
0x3 = Disable : Module is disabled and cannot be accessed
15-2 Reserved R 0h
1-0 MODULEMODE R/W 2h
Control the way mandatory clocks are managed.
0x0 = DISABLED : Module is disable by SW. Any OCP access to
module results in an error, except if resulting from a module wakeup
(asynchronous wakeup).
0x1 = RESERVED_1 : Reserved
0x2 = ENABLE : Module is explicitly enabled. Interface clock (if not
used for functions) may be gated according to the clock domain
state. Functional clocks are guarantied to stay present. As long as in
this configuration, power domain sleep transition cannot happen.
0x3 = RESERVED : Reserved
8.1.12.5 CM_DEVICE Registers
Table 8-164 lists the memory-mapped registers for the CM_DEVICE. All register offset addresses not
listed in Table 8-164 should be considered as reserved locations and the register contents should not be
modified.
Table 8-164. CM_DEVICE REGISTERS
Offset Acronym Register Name Section
0h CM_CLKOUT_CTRL This register provides the control over CLKOUT2 output Section 8.1.12.5.1
690
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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