CONTROL_MODULE Registers
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9.3.32 pwmss_ctrl Register (offset = 664h) [reset = 0h]
pwmss_ctrl is shown in Figure 9-35 and described in Table 9-42.
Figure 9-35. pwmss_ctrl Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved pwmss2_tbclken pwmss1_tbclken pwmss0_tbclken
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-42. pwmss_ctrl Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
2 pwmss2_tbclken R/W 0h Timebase clock enable for PWMSS2
1 pwmss1_tbclken R/W 0h Timebase clock enable for PWMSS1
0 pwmss0_tbclken R/W 0h Timebase clock enable for PWMSS0
796
Control Module SPRUH73H–October 2011–Revised April 2013
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