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7.3.5.20 PERF_CNT_CFG Register (offset = 88h) [reset = 10000h]
PERF_CNT_CFG is shown in Figure 7-110 and described in Table 7-130.
Figure 7-110. PERF_CNT_CFG Register
31 30 29 28 27 26 25 24
reg_cntr2_mconnid_e reg_cntr2_region_en Reserved
n
R/W-0h R/W-0h R-0h
23 22 21 20 19 18 17 16
Reserved reg_cntr2_cfg
R-0h R/W-1h
15 14 13 12 11 10 9 8
reg_cntr1_mconnid_e reg_cntr1_region_en Reserved
n
R/W-0h R/W-0h R-0h
7 6 5 4 3 2 1 0
Reserved reg_cntr1_cfg
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-130. PERF_CNT_CFG Register Field Descriptions
Bit Field Type Reset Description
31 reg_cntr2_mconnid_en R/W 0h
MConnID filter enable for Performance Counter 2 register.
30 reg_cntr2_region_en R/W 0h
Chip Select filter enable for Performance Counter 2 register.
29-20 Reserved R 0h
19-16 reg_cntr2_cfg R/W 1h Filter configuration for Performance Counter 2.
For details, see the table titled "Filter Configurations for Performance
Counters".
15 reg_cntr1_mconnid_en R/W 0h
MConnID filter enable for Performance Counter 1 register.
14 reg_cntr1_region_en R/W 0h
Chip Select filter enable for Performance Counter 1 register.
13-4 Reserved R 0h
3-0 reg_cntr1_cfg R/W 0h Filter configuration for Performance Counter 1.
For details, see the table titled "Filter Configurations for Performance
Counters".
445
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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