McASP Registers
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22.4.1.15 Receive Bit Stream Format Register (RFMT)
The receive bit stream format register (RFMT) configures the receive data format. The RFMT is shown in
Figure 22-53 and described in Table 22-26.
Figure 22-53. Receive Bit Stream Format Register (RFMT)
31 18 17 16
Reserved RDATDLY
R-0 R/W-0
15 14 13 12 8 7 4 3 2 0
RRVRS RPAD RPBIT RSSZ RBUSEL RROT
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-26. Receive Bit Stream Format Register (RFMT) Field Descriptions
Bit Field Value Description
31-18 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
17-16 RDATDLY 0-3h Receive bit delay.
0 0-bit delay. The first receive data bit, AXRn, occurs in same ACLKR cycle as the receive frame sync
(AFSR).
1h 1-bit delay. The first receive data bit, AXRn, occurs one ACLKR cycle after the receive frame sync
(AFSR).
2h 2-bit delay. The first receive data bit, AXRn, occurs two ACLKR cycles after the receive frame sync
(AFSR).
3h Reserved.
15 RRVRS Receive serial bitstream order.
0 Bitstream is LSB first. No bit reversal is performed in receive format bit reverse unit.
1 Bitstream is MSB first. Bit reversal is performed in receive format bit reverse unit.
14-13 RPAD 0-3h Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n]
= 0.
0 Pad extra bits with 0.
1h Pad extra bits with 1.
2h Pad extra bits with one of the bits from the word as specified by RPBIT bits.
3h Reserved.
12-8 RPBIT 0-1Fh RPBIT value determines which bit (as read by the CPU or DMA from RBUF[n]) is used to pad the extra
bits. This field only applies when RPAD = 2h.
0 Pad with bit 0 value.
1h-1Fh Pad with bit 1 to bit 31 value.
3850
Multichannel Audio Serial Port (McASP) SPRUH73H–October 2011–Revised April 2013
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