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Ethernet Subsystem Registers
14.5.9.19 C0_TX_STAT Register (offset = 48h) [reset = 0h]
C0_TX_STAT is shown in Figure 14-215 and described in Table 14-233.
SUBSYSTEM CORE 0 TX INTERRUPT MASKED INT STATUS REGISTER
Figure 14-215. C0_TX_STAT Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
C0_TX_STAT
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-233. C0_TX_STAT Register Field Descriptions
Bit Field Type Reset Description
31-8 Reserved R 0h
7-0 C0_TX_STAT R 0h Core 0 Transmit Masked Interrupt Status - Each bit in this read only
register corresponds to the bit in the Tx interrupt that is enabled and
generating an interrupt on C0_TX_PULSE .
1457
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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