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Power, Reset, and Clock Management
8.1.12.3.9 CLKSEL_TIMER1MS_CLK Register (offset = 28h) [reset = 0h]
CLKSEL_TIMER1MS_CLK is shown in Figure 8-146 and described in Table 8-155.
Selects the Mux select line for TIMER1 clock [warm reset insensitive]
Figure 8-146. CLKSEL_TIMER1MS_CLK Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-155. CLKSEL_TIMER1MS_CLK Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
2-0 CLKSEL R/W 0h
Selects the Mux select line for DMTIMER_1MS clock [warm reset
insensitive]
0x0 = SEL1 : Select CLK_M_OSC clock
0x1 = SEL2 : Select CLK_32KHZ clock
0x2 = SEL3 : Select TCLKIN clock
0x3 = SEL4 : Select CLK_RC32K clock
0x4 = SEL5 : Selects the CLK_32768 from 32KHz Crystal Osc
683
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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