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CONTROL_MODULE Registers
9.3.11 pll_clkinpulow_ctrl Register (offset = 458h) [reset = 0h]
pll_clkinpulow_ctrl is shown in Figure 9-14 and described in Table 9-21.
Figure 9-14. pll_clkinpulow_ctrl Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved ddr_pll_clkinpulow_sel disp_pll_clkinpulow_s mpu_dpll_clkinpulow_
el sel
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 9-21. pll_clkinpulow_ctrl Register Field Descriptions
Bit Field Type Reset Description
31-3 Reserved R 0h
2 ddr_pll_clkinpulow_sel R/W 0h 0 : Select CORE_CLKOUT_M6 clock as CLKINPULOW
1 : Select PER_CLKOUT_M2 clock as CLKINPULOW
1 disp_pll_clkinpulow_sel R/W 0h 0 : Select CORE_CLKOUT_M6 clock as CLKINPULOW
1 : Select PER_CLKOUT_M2 clock as CLKINPULOW
0 mpu_dpll_clkinpulow_sel R/W 0h 0 : Select CORE_CLKOUT_M6 clock as CLKINPULOW
1 : Select PER_CLKOUT_M2 clock as CLKINPULOW
773
SPRUH73H–October 2011–Revised April 2013 Control Module
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