Power, Reset, and Clock Management
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8.1.13.5.3 PRM_RSTST Register (offset = 8h) [reset = 1h]
PRM_RSTST is shown in Figure 8-181 and described in Table 8-200.
This register logs the global reset sources. Each bit is set upon release of the domain reset signal. Must
be cleared by software. [warm reset insensitive]
Figure 8-181. PRM_RSTST Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved ICEPICK_RST Reserved
R-0h R/W-0h R-0h
7 6 5 4 3 2 1 0
Reserved EXTERNAL_WARM_ WDT1_RST Reserved Reserved GLOBAL_WARM_SW GLOBAL_COLD_RST
RST _RST
R-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-200. PRM_RSTST Register Field Descriptions
Bit Field Type Reset Description
31-10 Reserved R 0h
9 ICEPICK_RST R/W 0h IcePick reset event.
This is a source of global warm reset initiated by the emulation.
[warm reset insensitive]
0x0 = 0x0 : No ICEPICK reset.
0x1 = 0x1 : IcePick reset has occurred.
8-6 Reserved R 0h
5 EXTERNAL_WARM_RST R/W 0h
External warm reset event [warm reset insensitive]
0x0 = 0x0 : No global warm reset.
0x1 = 0x1 : Global external warm reset has occurred.
4 WDT1_RST R/W 0h Watchdog1 timer reset event.
This is a source of global WARM reset.
[warm reset insensitive]
0x0 = 0x0 : No watchdog reset.
0x1 = 0x1 : watchdog reset has occurred.
3 Reserved R 0h
Reserved.
2 Reserved R/W 0h
Reserved.
1 GLOBAL_WARM_SW_RS R/W 0h
Global warm software reset event [warm reset insensitive]
T
0x0 = 0x0 : No global warm SW reset
0x1 = 0x1 : Global warm SW reset has occurred.
0 GLOBAL_COLD_RST R/W 1h
Power-on (cold) reset event [warm reset insensitive]
0x0 = 0x0 : No power-on reset.
0x1 = 0x1 : Power-on reset has occurred.
728
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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