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Functional Description
Figure 11-27. Data Sorting Example PaRAM Configuration
(a) EDMA Parameters
Parameter Contents Parameter
0090 0004h Channel Options Parameter (OPT)
Channel Source Address (SRC) Channel Source Address (SRC)
0400h 0004h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT)
Channel Destination Address (DST) Channel Destination Address (DST)
0010h 0001h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX)
0000h FFFFh BCNT Reload (BCNTRLD) Link Address (LINK)
0001h 1000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX)
0000h 0004h Reserved Count for 3rd Dimension (CCNT)
(b) Channel Options Parameter (OPT) Content
31 30 28 27 24 23 22 21 20 19 18 17 16
0 000 0000 1 0 0 1 00 00
PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC
15 12 11 10 8 7 4 3 2 1 0
0000 0 000 0000 0 1 0 0
TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM
11.3.19.4 Peripheral Servicing Example
The EDMA3 channel controller also services peripherals in the background of CPU operation, without
requiring any CPU intervention. Through proper initialization of the EDMA3 channels, they can be
configured to continuously service on-chip and off-chip peripherals throughout the device operation. Each
event available to the EDMA3 has its own dedicated channel, and all channels operate simultaneously.
The only requirements are to use the proper channel for a particular transfer and to enable the channel
event in the event enable register (EER). When programming an EDMA3 channel to service a peripheral,
it is necessary to know how data is to be presented to the processor. Data is always provided with some
kind of synchronization event as either one element per event (non-bursting) or multiple elements per
event (bursting).
11.3.19.4.1 Non-bursting Peripherals
Non-bursting peripherals include the on-chip multichannel audio serial port (McASP) and many external
devices, such as codecs. Regardless of the peripheral, the EDMA3 channel configuration is the same.
The McASP transmit and receive data streams are treated independently by the EDMA3. The transmit
and receive data streams can have completely different counts, data sizes, and formats. Figure 11-28
shows servicing incoming McASP data.
To transfer the incoming data stream to its proper location in DDR memory, the EDMA3 channel must be
set up for a 1D-to-1D transfer with A-synchronization. Because an event (AREVT) is generated for every
word as it arrives, it is necessary to have the EDMA3 issue the transfer request for each element
individually. Figure 11-29 shows the parameters for this transfer. The source address of the EDMA3
channel is set to the data port address(DAT) for McASP, and the destination address is set to the start of
the data block in DDR. Because the address of serializer buffer is fixed, the source B index is cleared to 0
(no modification) and the destination B index is set to 01b (increment).
Based on the premise that serial data is typically a high priority, the EDMA3 channel should be
programmed to be on queue 0.
923
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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