DMTimer 1ms
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20.2.5.12 TMAR Register (offset = 38h) [reset = 0h]
TMAR is shown in Figure 20-46 and described in Table 20-47.
This register holds the match value to be compared with the counter's value
Figure 20-46. TMAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMPARE_VALUE
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-47. TMAR Register Field Descriptions
Bit Field Type Reset Description
31-0 COMPARE_VALUE R/W 0h
The value of the match register
3612
Timers SPRUH73H–October 2011–Revised April 2013
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