McASP Registers
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22.4.1.35 Transmit Clock Check Control Register (XCLKCHK)
The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit.
The XCLKCHK is shown in Figure 22-73 and described in Table 22-46.
Figure 22-73. Transmit Clock Check Control Register (XCLKCHK)
31 24 23 16
XCNT XMAX
R-0 R/W-0
15 8 7 4 3 0
XMIN Reserved XPS
R/W-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-46. Transmit Clock Check Control Register (XCLKCHK) Field Descriptions
Bit Field Value Description
31-24 XCNT 0 Transmit clock count value (from previous measurement). The clock circuit continually counts the
number of system clocks for every 32 transmit high-frequency master clock (AHCLKX) signals, and
stores the count in XCNT until the next measurement is taken.
23-16 XMAX 0-FFh Transmit clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for
the clock check counter after 32 transmit high-frequency master clock (AHCLKX) signals have been
received. If the current counter value is greater than XMAX after counting 32 AHCLKX signals,
XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic.
15-8 XMIN 0-FFh Transmit clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for
the clock check counter after 32 transmit high-frequency master clock (AHCLKX) signals have been
received. If XCNT is less than XMIN after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The
comparison is performed using unsigned arithmetic.
7-4 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
3-0 XPS 0-Fh Transmit clock check prescaler value.
0 McASP system clock divided by 1.
1h McASP system clock divided by 2.
2h McASP system clock divided by 4.
3h McASP system clock divided by 8.
4h McASP system clock divided by 16.
5h McASP system clock divided by 32.
6h McASP system clock divided by 64.
7h McASP system clock divided by 128.
8h McASP system clock divided by 256.
9h-Fh Reserved.
3872
Multichannel Audio Serial Port (McASP) SPRUH73H–October 2011–Revised April 2013
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