Texas Instruments AM335 Series Technical Reference Manual

L3F
L3S
SGX530
128
LCD
Ctrl
32
MPUSS
(Cortex A8)
128
64
TPTC
3 Channels
128
R0
128
W0
128
R1
128
W1
128
R2
128
W2
2 Port
GEMAC
Switch
32
Debug
Acc
Port
32
PRU-ICSS
32
32
0 1
IEEE
1500
32
USB
32
32
0 1
EMIF
128
TPTC CFG
32
32 32
0 1 2
TPCC
32
OCMC
RAM
64
SGX530
64
OCP-WP
32
32
DebugSS
32
FR
L4_WKUP
L4_FAST
32
L4_PER
32 32 32 32
ADC
TSC
32
McASP0
32
McASP1
32
GPMC
32
USB
32
MMCHS2
32
L4_WKUP
32
www.ti.com Introduction
Figure 10-1. L3 Topology
10.1.2.2 L3 Port Mapping
Each initiator and target core is connected to the L3 interconnect through a Network Interface Unit (NIU).
The NIUs act as entry and exit points to the L3 Network on Chip – converting between the IP’s OCP
protocol and the NoC’s internal protocol, and also include various programming registers. All ports are
single threaded with tags used to enable pipelined transactions. The interconnect includes:
Initiator Ports:
• L3F
– Cortex A8 MPUSS 128-bit initiator port0 and 64-bit initiator port1
– SGX530 128-bit initiator port
– 3 TPTC 128-bit read initiator ports
– 3 TPTC 128-bit write initiator ports
– LCDC 32-bit initiator port
– 2 PRU-ICSS1 32-bit initiator ports
– 2 port Gigabit Ethernet Switch (2PGSW) 32-bit initiator port
– Debug Subsystem 32-bit initiator port
• L3S
– USB 32-bit CPPI DMA initiator port
– USB 32-bit Queue Manager initiator port
– P1500 32-bit initiator port
Target Ports:
• L3F
– EMIF 128-bit target port
– 3 TPTC CFG 32-bit target ports
– TPCC CFG 32-bit target port
– OCM RAM0 64-bit target port
– DebugSS 32-bit target port
– SGX530 64-bit target port
– L4_FAST 32-bit target port
• L3S
– 4 L4_PER peripheral 32-bit target ports
– GPMC 32-bit target port
– McASP0 32-bit target port
865
SPRUH73H–October 2011–Revised April 2013 Interconnects
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Texas Instruments AM335 Series Specifications

General

Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English