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7.3.5.29 ZQ_CONFIG Register (offset = C8h) [reset = 0h]
ZQ_CONFIG is shown in Figure 7-119 and described in Table 7-139.
Figure 7-119. ZQ_CONFIG Register
31 30 29 28 27 26 25 24
reg_zq_cs1en reg_zq_cs0en reg_zq_dualcalen reg_zq_sfexiten Reserved
R/W-0h R/W-0h R/W-0h R/W-0h R-0h
23 22 21 20 19 18 17 16
Reserved reg_zq_zqinit_mult reg_zq_zqcl_mult
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
reg_zq_refinterval
R/W-0h
7 6 5 4 3 2 1 0
reg_zq_refinterval
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-139. ZQ_CONFIG Register Field Descriptions
Bit Field Type Reset Description
31 reg_zq_cs1en R/W 0h
Writing a 1 enables ZQ calibration for CS1.
30 reg_zq_cs0en R/W 0h
Writing a 1 enables ZQ calibration for CS0.
29 reg_zq_dualcalen R/W 0h ZQ Dual Calibration enable.
Allows both ranks to be ZQ calibrated simultaneously.
Setting this bit requires both chip selects to have a seerate
calibration resistor per device.
28 reg_zq_sfexiten R/W 0h ZQCL on Self Refresh, Active Power-Down, and Precharge Power-
Down exit enable.
Writing a 1 enables the issuing of ZQCL on Self-Refresh, Active
Power-Down, and Precharge Power-Down exit.
27-20 Reserved R 0h
19-18 reg_zq_zqinit_mult R/W 0h
Indicates the number of ZQCL intervals that make up a ZQINIT
interval, minus one.
17-16 reg_zq_zqcl_mult R/W 0h Indicates the number of ZQCS intervals that make up a ZQCL
interval, minus one.
ZQCS interval is defined by reg_zq_zqcs in SDRAM Timing 3
Register.
15-0 reg_zq_refinterval R/W 0h Number of refresh periods between ZQCS commans.
This field supports between one refresh period to 256 ms between
ZQCS calibration commands.
Refresh period is defined by reg_refresh_rate in SDRAM Refresh
Control register.
454
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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