Texas Instruments AM335 Series Technical Reference Manual

www.ti.com EDMA3 Registers
11.4.1.2 Error Registers
The EDMA3CC contains a set of registers that provide information on missed DMA and/or QDMA events,
and instances when event queue thresholds are exceeded. If any of the bits in these registers is set, it
results in the EDMA3CC generating an error interrupt.
11.4.1.2.1 Event Missed Registers (EMR/EMRH)
For a particular DMA channel, if a second event is received prior to the first event getting cleared/serviced,
the bit corresponding to that channel is set/asserted in the event missed registers (EMR/EMRH). All
trigger types are treated individually, that is, manual triggered (ESR/ESRH), chain triggered (CER/CERH),
and event triggered (ER/ERH) are all treated separately. The EMR/EMRH bits for a channel are also set if
an event on that channel encounters a NULL entry (or a NULL TR is serviced). If any EMR/EMRH bit is
set (and all errors, including bits in other error registers (QEMR, CCERR) were previously cleared), the
EDMA3CC generates an error interrupt. For details on EDMA3CC error interrupt generation, see Error
Interrupts.
The EMR is shown in Figure 11-50 and described in Table 11-35. The EMRH is shown in Figure 11-51
and described in Table 11-36.
Figure 11-50. Event Missed Register (EMR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 11-35. Event Missed Register (EMR) Field Descriptions
Bit Field Value Description
31-0 En Channel 0-31 event missed. En is cleared by writing a 1 to the corresponding bit in the event missed clear
register (EMCR).
0 No missed event.
1 Missed event occurred.
Figure 11-51. Event Missed Register High (EMRH)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E63 E62 E61 E60 E59 E58 E57 E56 E55 E54 E53 E52 E51 E50 E49 E48
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E47 E46 E45 E44 E43 E42 E41 E40 E39 E38 E37 E36 E35 E34 E33 E32
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 11-36. Event Missed Register High (EMRH) Field Descriptions
Bit Field Value Description
31-0 En Channel 32–63 event missed. En is cleared by writing a 1 to the corresponding bit in the event missed
clear register high (EMCRH).
0 No missed event.
1 Missed event occurred.
951
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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Texas Instruments AM335 Series Specifications

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