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Ethernet Subsystem Registers
14.5.6.20 P1_TX_IN_CTL Register (offset = 110h) [reset = 80040C0h]
P1_TX_IN_CTL is shown in Figure 14-140 and described in Table 14-155.
CPSW PORT 1 TRANSMIT FIFO CONTROL
Figure 14-140. P1_TX_IN_CTL Register
31 30 29 28 27 26 25 24
Reserved HOST_BLKS_REM
R/W-8h
23 22 21 20 19 18 17 16
TX_RATE_EN Reserved TX_IN_SEL
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
TX_BLKS_REM Reserved TX_PRI_WDS
R/W-4h R/W-C0h
7 6 5 4 3 2 1 0
TX_PRI_WDS
R/W-C0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-155. P1_TX_IN_CTL Register Field Descriptions
Bit Field Type Reset Description
27-24 HOST_BLKS_REM R/W 8h Transmit FIFO Blocks that must be free before a non rate-limited
CPDMA channel can begin sending a packet to the FIFO.
23-20 TX_RATE_EN R/W 0h
Transmit FIFO Input Rate Enable
17-16 TX_IN_SEL R/W 0h Transmit FIFO Input Queue Type Select
00 - Normal priority mode
01 - reserved
10 - Rate Limit mode
11 - reserved
15-12 TX_BLKS_REM R/W 4h Transmit FIFO Input Blocks to subtract in dual mac mode and blocks
to subtract on non rate-limited traffic in rate-limit mode.
9-0 TX_PRI_WDS R/W C0h
Transmit FIFO Words in queue
1377
SPRUH73H–October 2011–Revised April 2013 Ethernet Subsystem
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