Ethernet Subsystem Registers
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14.5.2.17 TX_PRI5_RATE Register (offset = 44h) [reset = 0h]
TX_PRI5_RATE is shown in Figure 14-45 and described in Table 14-56.
CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 5 RATE
Figure 14-45. TX_PRI5_RATE Register
31 30 29 28 27 26 25 24
Reserved PRIN_IDLE_CNT
R-0h R/W-0h
23 22 21 20 19 18 17 16
PRIN_IDLE_CNT
R/W-0h
15 14 13 12 11 10 9 8
Reserved PRIN_SEND_CNT
R-0h R/W-0h
7 6 5 4 3 2 1 0
PRIN_SEND_CNT
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-56. TX_PRI5_RATE Register Field Descriptions
Bit Field Type Reset Description
31-30 Reserved R 0h
29-16 PRIN_IDLE_CNT R/W 0h Priority (
7:0) idle count
15-14 Reserved R 0h
13-0 PRIN_SEND_CNT R/W 0h Priority (
7:0) send count
1276
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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