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Pulse-Width Modulation Subsystem (PWMSS)
15.1.3.2 SYSCONFIG Register (offset = 4h) [reset = 28h]
SYSCONFIG is shown in Figure 15-3 and described in Table 15-7.
The system configuration register is used for clock management configuration.
Figure 15-3. SYSCONFIG Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved Reserved IDLEMODE FREEEMU SOFTRESET
R-0h R-0h R/W-2h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 15-7. SYSCONFIG Register Field Descriptions
Bit Field Type Reset Description
31-6 Reserved R 0h
5-4 Reserved R 0h
3-2 IDLEMODE R/W 2h Configuration of the local target state management mode.
By definition, target can handle read/write transaction as long as it is
out of IDLE state.
0x0 = Force-idle mode: local target's idle state follows
(acknowledges) the system's idle requests unconditionally, i.e.
regardless of the IP module's internal requirements. Backup mode,
for debug only.
0x1 = No-idle mode: local target never enters idle state. Backup
mode, for debug only.
0x2 = Smart-idle mode: local target's idle state eventually follows
(acknowledges) the system's idle requests, depending on the IP
module's internal requirements. IP module shall not generate (IRQ-
or DMA-request-related) wakeup events.
0x3 = Reserved.
1 FREEEMU R/W 0h
Sensitivity to emulation (debug) suspend input signal.
0x0 = IP module is sensitive to emulation suspend.
0x1 = IP module is not sensitive to emulation suspend.
0 SOFTRESET R/W 0h
Software reset (optional)
1491
SPRUH73H–October 2011–Revised April 2013 Pulse-Width Modulation Subsystem (PWMSS)
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