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EDMA3 Registers
11.4.1.8 QDMA Registers
The following sets of registers control the QDMA channels in the EDMA3CC. The QDMA channels (with
the exception of the QDMA queue number register) consist of a set of registers, each of which have a bit
location. Each bit position corresponds to a QDMA channel number. The QDMA channel registers are
accessible via read/writes to the global address range. They are also accessible via read/writes to the
shadow address range. The read/write accessibility in the shadow region address region is controlled by
the QDMA region access registers (QRAEn/QRAEHn). EDMA3 Channel Controller Regions details
shadow region/global region usage.
11.4.1.8.1 QDMA Event Register (QER)
The QDMA event register (QER) channel n bit is set (En = 1) when the CPU or any EDMA3 programmer
(including EDMA3) performs a write to the trigger word (using the QDMA channel mapping register
(QCHMAPn)) in the PaRAM entry associated with QDMA channel n (which is also programmed using
QCHMAPn). The En bit is also set when the EDMA3CC performs a link update on a PaRAM address that
matches the QCHMAPn settings. The QDMA event is latched only if the QDMA event enable register
(QEER) channel n bit is also enabled (QEER.En = 1). Once a bit is set in QER, then the corresponding
QDMA event (auto-trigger) is evaluated by the EDMA3CC logic for an associated transfer request
submission to the transfer controllers. For additional conditions that can lead to the setting of QER bits,
see EDMA Overview.
The setting of an event is a higher priority relative to clear operations (via hardware). If set and clear
conditions occur concurrently, the set condition wins. If the event was previously set, then the QDMA
event missed register (QEMR) would be set because an event is lost. If the event was previously clear,
then the event remains set and is prioritized for submission to the event queues.
The set bits in QER are only cleared when the transfer request associated with the corresponding
channels has been processed by the EDMA3CC and submitted to the transfer controller. If the En bit is
already set and a QDMA event for the same QDMA channel occurs prior to the original being cleared,
then the second missed event is latched in QEMR (En = 1).
The QER is shown in Figure 11-99 and described in Table 11-83.
Figure 11-99. QDMA Event Register (QER)
31 16
Reserved
R-0
15 7 6 5 4 3 2 1 0
Reserved E7 E6 E5 E4 E3 E2 E1 E0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 11-83. QDMA Event Register (QER) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
7-0 En QDMA event for channels 0-7.
0 No effect.
1 Corresponding QDMA event is prioritized versus other pending DMA/QDMA events for submission to
the EDMA3TC.
987
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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