I2C Registers
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21.4.1.22 I2C_PSC Register (offset = B0h) [reset = 0h]
I2C_PSC is shown in Figure 21-37 and described in Table 21-30.
CAUTION: During an active mode (I2C_EN bit in I2C_CON register is set to 1), no modification must be
done in this register. Changing it may result in an unpredictable behavior. This register is used to specify
the internal clocking of the I2C peripheral core.
Figure 21-37. I2C_PSC Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
PSC
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 21-30. I2C_PSC Register Field Descriptions
Bit Field Type Reset Description
31-8 Reserved R 0h
7-0 PSC R/W 0h Fast/Standard mode prescale sampling clock divider value.
The core uses this
8-bit value to divide the system clock (SCLK) and generates its own
internal sampling clock (ICLK) for Fast and Standard operation
modes.
The core logic is sampled at the clock rate of the system clock for
the module divided by (PSC + 1).
Value after reset is low (all 8 bits).
0x0 = Divide by 1
0x1 = Divide by 2
0xFF = Divide by 256
3754
I2C SPRUH73H–October 2011–Revised April 2013
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