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7.3.5.31 RDWR_LVL_RMP_CTRL Register (offset = D8h) [reset = 0h]
Read-Write Leveling Ramp Control Register
Read-Write Leveling Ramp Control Register is shown in Figure 7-121 and described in Table 7-141.
Figure 7-121. Read-Write Leveling Ramp Control Register
31 30 29 28 27 26 25 24
REG_RDWRLVL_EN REG_RDWRLVLINC_RMP_PRE
R/W-
23 22 21 20 19 18 17 16
REG_RDLVLINC_RMP_INT
R/W-
15 14 13 12 11 10 9 8
REG_RDLVLGATEINC_RMP_INT
R/W-
7 6 5 4 3 2 1 0
REG_WRLVLINC_RMP_INT
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-141. Read-Write Leveling Ramp Control Register Field Descriptions
Bit Field Type Reset Description
31 REG_RDWRLVL_EN R/W Read-Write Leveling enable.
Set 1 to enable leveling.
Set 0 to disable leveling.
30-24 REG_RDWRLVLINC_RM Incremental leveling pre-scalar in number of refresh periods during
P_PRE ramp window.
The value programmed is minus one the required value.
Refresh period is defined by reg_refresh_rate in SDRAM Refresh
Control register.
23-16 REG_RDLVLINC_RMP_I R/W Incremental read data eye training interval during ramp window.
NT Number of reg_rdwrlvlinc_rmp_pre intervals between incremental
read data eye training.
A value of 0 will disable incremental read data eye training during
ramp window.
15-8 REG_RDLVLGATEINC_R R/W Incremental read DQS gate training interval during ramp window.
MP_INT Number of reg_rdwrlvlinc_rmp_pre intervals between incremental
read DQS gate training.
A value of 0 will disable incremental read DQS gate training during
ramp window.
7-0 REG_WRLVLINC_RMP_I Incremental write leveling interval during ramp window.
NT Number of reg_rdwrlvlinc_rmp_pre intervals between incremental
write leveling.
A value of 0 will disable incremental write leveling during ramp
window.
456
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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